Tole Sutikno
Associate Professor, Dept. of Electrical Eng., Universitas Ahmad Dahlan

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FPGA and Embedded System



Definitions of Embedded system on the Web:

· An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, often with real-time computing ...
en.wikipedia.org/wiki/Embedded_system

· A system containing a processor where the processor is not generally reprogrammable by the end user. For example, a cell phone containing a DSP ...
www.bdti.com/articles/dspdictionary.html

· A computer system that is a component of a larger machine or system. Embedded systems can respond to events in real time. ...
publib.boulder.ibm.com/infocenter/pvcvoice/51x/topic/com.ibm.websphere.wvs.doc/wvs/glossary.html

· A combination of computer hardware and software, and perhaps additional mechanical or other parts, designed to perform a dedicated function. ...
www.actc-control.com/glossary/glossary_E.asp

· A device, usually with a singular function such as controlling a piece of machinery on an assembly line, that contains a microprocessor. Inability to handle information such as four-digit dates or leap days can cause these systems that depend on them to shut down in the year 2000.
www.crm.mb.ca/guide/glossary.html

· Hardware and software that forms a component of some larger system and is expected to function without human intervention. ...
techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi




VHDL Cheat Sheet – Combinational Logic

Libraries

ALWAYS start each VHDL file with the following 2 lines

library ieee;

use ieee.std_logic_1164.all;

Data Types

Two most common: std_logic, std_logic_vector( downto 0)

Entities

Defines a black-box interface for your module

entity MyEntity is

port ( a, b : in std_logic;

c : out std_logic);

end entity;

Architectures

Defines your implementation of your entity

Include any signal declarations before ‘begin’

architecture main of MyEntity is

signal ;

begin

end architecture;

Component Declaration

Any architectures that use an external component must have a component declaration

architecture main of MyEntity is

component DFF

port( d : in std_logic;

q : out std_logic);

end component;

signal EntityD, EntityQ : std_logic;

begin

DFF_1 : DFF

Port map (d => EntityD, q => EntityQ);

end architecture;

Concurrent Assignment

Describes a wired connection

a <= b and c;

The following 2 can only be written OUTSIDE a process

Selected Assignment

With Sel select

Y <= A when “00”,

B when “01”,

C when “10”,

D when others;

Conditional Assignment

Y <= A when Sel = “00” else

B when Sel = “01” else

C when Sel = “10” else

D when others;

Combinational Processes

Another way to describe combinational logic

A process is combinational if it doesn’t infer any registers

process()

begin

end process;

The following 2 can only be written INSIDE a process

If-Then-Else

process(a)

begin

if a = ‘0’ then

q <= ‘0’

else

q <= ‘1’

end if;

end process;

Case Statement

process(a)

begin

case a

when ‘0’ => q <= ‘0’;

when others => q <= ‘1’;

end case;

end process;

Sequential Processes

Describes sequential logic

A process is sequential if it infers at least one register

process(clk)

begin

if rising_edge(clk) then

end if;

end process;



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Tole Sutikno - Electrical Engineering Department Copyright 2013