Tole Sutikno
Associate Professor, Dept. of Electrical Eng., Universitas Ahmad Dahlan

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Vhdl step by step





1. Counter (Pencacah)


-- Example 1, filename: count8bit
-- Counter akan mencacah dari 0,1... 255 kemudian reset lagi

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity count18bit is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (7 downto 0));
end count8bit;

architecture Behavioral of count8bit is
signal qint, q : std_logic_vector( 7 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q; -- output couter
end Behavioral;


-- Example 2, filename: count52
-- Up counter (pencacah 52)
-- Mencacah dari 0, 1...51 dan kemudian mulai lagi dari 0

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity count52 is
port (clk : in STD_LOGIC;
count : out std_logic_vector (5 downto 0);
clr : in STD_LOGIC; -- clr=1 system enable, clr=0 system disable
clkout : out STD_LOGIC);
end count52;

architecture behaviour of count52 is
signal q : std_logic;
signal qint1, qint2: std_logic_vector (5 downto 0);

begin
qint1 <= "000000" when q='1' else std_logic_vector(unsigned(qint2)+1); -- 6 bit
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 51) else '0';
count <=qint2; -- counter modulus 52 is displayed
end behaviour;


-- Example 3, filename: count52down
-- Down counter (pencacah 52)
-- Mencacah dari 63, 62..12, 63,62...12,63.....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity count52_downv2 is
port (clk : in STD_LOGIC;
count : out std_logic_vector (5 downto 0);
clr : in STD_LOGIC; -- clr=1 system enable, clr=0 system disable
clkout : out STD_LOGIC);
end count52_downv2;

architecture behaviour of count52_downv2 is
signal q : std_logic;
signal qint1, qint2: std_logic_vector (5 downto 0);

begin
qint1 <= "111111" when q='1' else std_logic_vector(unsigned(qint2)-1); -- 6 bit
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 12) else '0'; -- counter from 63,62...12
count <=qint2; -- counter modulus 52 is displayed
end behaviour;



2. Clock divider

-- Example 1, filename: mod52v_en
-- Pembagi Frekuensi Clock yang dilengkapi fungsi enable dan disable
-- Modulus 52 (Clock Divider)
-- For example clock input= 33.33 Mhz --> Freq_out=33.33Mhz:52=641.026khz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mod52v_en is
port (clk : in STD_LOGIC;
-- count : out std_logic_vector (5 downto 0);
clr : in STD_LOGIC; -- clr=1 system enable, clr=0 system disable
clkout : out STD_LOGIC);
end mod52v_en;

architecture behaviour of mod52v_en is
signal q : std_logic;
signal qint1, qint2: std_logic_vector (5 downto 0);

begin
qint1 <= "000000" when q='1' else std_logic_vector(unsigned(qint2)+1); -- 6 bit
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 52) else '0';

clkout <= q when clr='1' else '0'; -- if it is wanted to use enable/disable, if not just write "clkout <= q"
-- count <=qint1; -- counter modulus 52 is not displayed
end behaviour;




-- Example 2, file name: mod1852v
-- Modulus 1852 (Clock Divider)
-- Input: 33.33 Mhz ==> output 33.33Mhz:1852=18Khz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mod1852v is
port (clk : in STD_LOGIC;
-- count : out std_logic_vector (10 downto 0);
clkout : out STD_LOGIC);
end mod1852v;

architecture behaviour of mod1852v is
signal q : std_logic;
signal qint1, qint2: std_logic_vector (10 downto 0);

begin
qint1 <= "00000000000" when q='1' else std_logic_vector(unsigned(qint2)+1); -- 11 bit
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 1852) else '0';
clkout <= q;
-- count <=qint1; -- counter modulus 1852 is not displayed
end behaviour;



3. Blank Time (Dead Time)

-- Example 1

-- Clock FPGA APEX20KE=33.33Mhz==>t=30ns
-- This deadtime is designed 4*modulus17*t=4*17*30ns=2040ns=2.04microsecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity deadtime is
Port ( clock : in STD_LOGIC;
Sin : in STD_LOGIC;
Supper : out STD_LOGIC;
Slower : out STD_LOGIC);
end deadtime;

architecture behavioral of deadtime is
signal a,c: std_logic_vector( 15 downto 0);
signal d : std_logic;


-- The deadtime's entity is supported 5 entity unit
begin
U1: entity work.mod17(Behavioral) port map(clk=>clock,clkout=>d);
U2: entity work.upper_counter(Behavioral) port map(clk=>d,clear=>Sin,uc=>a);
U3: entity work.lowr_counter(Behavioral) port map(clk=>d,clear=>Sin,lc=>c);
U4: entity work.comp1(Behavioral) port map(Cin=>a,Cout=>Supper);
U5: entity work.comp2(Behavioral) port map(Cin=>c,Cout=>Slower);
end Behavioral;


-- U1: First entity unit => counter mod17 (clock divider)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity mod17 is
Port ( clk : in STD_LOGIC;
clkout : out STD_LOGIC);
end mod17;

architecture Behavioral of mod17 is
signal q : std_logic;
signal qint1,qint2 : std_logic_vector ( 4 downto 0);
begin
qint1 <= "00000" when q='1' else std_logic_vector(unsigned(qint2)+1);
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 17) else '0';
clkout <= q;
end Behavioral;
-- ending U1


-- U2: Second entity unit => upper_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity upper_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (15 downto 0));
end upper_counter;

architecture Behavioral of upper_counter is
signal qint, q : std_logic_vector( 15 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q;
end Behavioral;
-- ending U2


-- U3: Third entity unit => lower counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity lowr_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
lc : out STD_LOGIC_VECTOR (15 downto 0));
end lowr_counter;

architecture Behavioral of lowr_counter is
signal qint, q : std_logic_vector( 15 downto 0);
begin
qint <= (others=>'0') when clear ='1' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
lc<= q;
end Behavioral;
-- ending U3


-- U4: Fourth entity unit => comparator for s_upper (upper leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity comp1 is
Port ( Cin : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC);
end comp1;

architecture Behavioral of comp1 is
begin
Cout <= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U4


-- U5: Fifth entity unit => comparator for s_lower (lower leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity comp2 is
Port ( Cin : in STD_LOGIC_VECTOR (15 downto 0);
Cout : out STD_LOGIC);
end comp2;

architecture Behavioral of comp2 is
begin
Cout<= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U5



-- Example 2

-- Clock FPGA APEX20KE=33.33Mhz==>t=30ns
-- This deadtime is designed 4*modulus17*t=4*17*30ns=2040ns=2microsecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity deadtimev2 is
Port ( clock : in STD_LOGIC;
Sin : in STD_LOGIC;
Supper : out STD_LOGIC;
Slower : out STD_LOGIC);
end deadtimev2;

architecture behavioral of deadtimev2 is
signal a,c: std_logic_vector(6 downto 0);
signal d : std_logic;


-- The deadtime's entity is supported 5 entity unit
begin
U1: entity work.mod17(Behavioral) port map(clk=>clock,clkout=>d);
U2: entity work.upper_counter(Behavioral) port map(clk=>d,clear=>Sin,uc=>a);
U3: entity work.lowr_counter(Behavioral) port map(clk=>d,clear=>Sin,lc=>c);
U4: entity work.comp1(Behavioral) port map(Cin=>a,Cout=>Supper);
U5: entity work.comp2(Behavioral) port map(Cin=>c,Cout=>Slower);
end Behavioral;


-- U1: First entity unit => counter mod17 (clock divider)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity mod17 is
Port ( clk : in STD_LOGIC;
clkout : out STD_LOGIC);
end mod17;

architecture Behavioral of mod17 is
signal q : std_logic;
signal qint1,qint2 : std_logic_vector ( 4 downto 0);
begin
qint1 <= "00000" when q='1' else std_logic_vector(unsigned(qint2)+1);
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 17) else '0';
clkout <= q;
end Behavioral;
-- ending U1


-- U2: Second entity unit => upper_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity upper_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (6 downto 0));
end upper_counter;

architecture Behavioral of upper_counter is
signal qint, q : std_logic_vector( 6 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q;
end Behavioral;
-- ending U2


-- U3: Third entity unit => lower counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity lowr_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
lc : out STD_LOGIC_VECTOR (6 downto 0));
end lowr_counter;

architecture Behavioral of lowr_counter is
signal qint, q : std_logic_vector( 6 downto 0);
begin
qint <= (others=>'0') when clear ='1' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
lc<= q;
end Behavioral;
-- ending U3


-- U4: Fourth entity unit => comparator for s_upper (upper leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity comp1 is
Port ( Cin : in STD_LOGIC_VECTOR (6 downto 0);
Cout : out STD_LOGIC);
end comp1;

architecture Behavioral of comp1 is
begin
Cout <= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U4


-- U5: Fifth entity unit => comparator for s_lower (lower leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity comp2 is
Port ( Cin : in STD_LOGIC_VECTOR (6 downto 0);
Cout : out STD_LOGIC);
end comp2;

architecture Behavioral of comp2 is
begin
Cout<= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U5


-- Example 3

-- Clock FPGA APEX20KE=33.33Mhz==>t=30ns
-- This deadtime is designed 4*modulus17*t=4*17*30ns=
2040ns=2microsecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity deadtimev3 is
Port ( clock : in STD_LOGIC;
Sin : in STD_LOGIC;
Supper : out STD_LOGIC;
Slower : out STD_LOGIC);
end deadtimev3;

architecture behavioral of deadtimev3 is
signal a,c: std_logic_vector(5 downto 0);
signal d : std_logic;


-- The deadtime's entity is supported 5 entity unit
begin
U1: entity work.mod17(Behavioral) port map(clk=>clock,clkout=>d);
U2: entity work.upper_counter(Behavioral) port map(clk=>d,clear=>Sin,uc=>a);
U3: entity work.lowr_counter(Behavioral) port map(clk=>d,clear=>Sin,lc=>c);
U4: entity work.comp1(Behavioral) port map(Cin=>a,Cout=>Supper);
U5: entity work.comp2(Behavioral) port map(Cin=>c,Cout=>Slower);
end Behavioral;


-- U1: First entity unit => counter mod17 (clock divider)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity mod17 is
Port ( clk : in STD_LOGIC;
clkout : out STD_LOGIC);
end mod17;

architecture Behavioral of mod17 is
signal q : std_logic;
signal qint1,qint2 : std_logic_vector ( 4 downto 0);
begin
qint1 <= "00000" when q='1' else std_logic_vector(unsigned(qint2)+1);
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 17) else '0';
clkout <= q;
end Behavioral;
-- ending U1


-- U2: Second entity unit => upper_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity upper_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (5 downto 0));
end upper_counter;

architecture Behavioral of upper_counter is
signal qint, q : std_logic_vector(5 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q;
end Behavioral;
-- ending U2


-- U3: Third entity unit => lower counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity lowr_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
lc : out STD_LOGIC_VECTOR (5 downto 0));
end lowr_counter;

architecture Behavioral of lowr_counter is
signal qint, q : std_logic_vector(5 downto 0);
begin
qint <= (others=>'0') when clear ='1' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
lc<= q;
end Behavioral;
-- ending U3


-- U4: Fourth entity unit => comparator for s_upper (upper leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity comp1 is
Port ( Cin : in STD_LOGIC_VECTOR (5 downto 0);
Cout : out STD_LOGIC);
end comp1;

architecture Behavioral of comp1 is
begin
Cout <= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U4


-- U5: Fifth entity unit => comparator for s_lower (lower leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity comp2 is
Port ( Cin : in STD_LOGIC_VECTOR (5 downto 0);
Cout : out STD_LOGIC);
end comp2;

architecture Behavioral of comp2 is
begin
Cout<= '1' when (unsigned(Cin) > 4) else '0';
end Behavioral;
-- ending U5


-- Example 4

-- Clock FPGA APEX20KE=33.33Mhz==>t=30ns
-- This deadtime is designed 4*modulus17*t=4*17*30ns=
2040ns=2microsecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity deadtimev4 is
Port ( clock : in STD_LOGIC;
Sin : in STD_LOGIC;
Supper : out STD_LOGIC;
Slower : out STD_LOGIC);
end deadtimev4;

architecture behavioral of deadtimev4 is
signal a,c: std_logic_vector(3 downto 0);
signal d : std_logic;


-- The deadtime's entity is supported 5 entity unit
begin
U1: entity work.mod17(Behavioral) port map(clk=>clock,clkout=>d);
U2: entity work.upper_counter(Behavioral) port map(clk=>d,clear=>Sin,uc=>a);
U3: entity work.lowr_counter(Behavioral) port map(clk=>d,clear=>Sin,lc=>c);
U4: entity work.comp1(Behavioral) port map(Cin=>a,Cout=>Supper);
U5: entity work.comp2(Behavioral) port map(Cin=>c,Cout=>Slower);
end Behavioral;


-- U1: First entity unit => counter mod17 (clock divider)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity mod17 is
Port ( clk : in STD_LOGIC;
clkout : out STD_LOGIC);
end mod17;

architecture Behavioral of mod17 is
signal q : std_logic;
signal qint1,qint2 : std_logic_vector (6 downto 0);
begin
qint1 <= "0000000" when q='1' else std_logic_vector(unsigned(qint2)+1);
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 68) else '0'; -- changed mod17 to mod(17*4) =mod68;
clkout <= q;
end Behavioral;
-- ending U1


-- U2: Second entity unit => upper_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity upper_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (3 downto 0));
end upper_counter;

architecture Behavioral of upper_counter is
signal qint, q : std_logic_vector(3 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q;
end Behavioral;
-- ending U2


-- U3: Third entity unit => lower counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity lowr_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
lc : out STD_LOGIC_VECTOR (3 downto 0));
end lowr_counter;

architecture Behavioral of lowr_counter is
signal qint, q : std_logic_vector(3 downto 0);
begin
qint <= (others=>'0') when clear ='1' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
lc<= q;
end Behavioral;
-- ending U3


-- U4: Fourth entity unit => comparator for s_upper (upper leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity comp1 is
Port ( Cin : in STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end comp1;

architecture Behavioral of comp1 is
begin
Cout <= '1' when (unsigned(Cin) > 1) else '0'; -- (Cin) > 4 is changed with (Cin) > 1
end Behavioral;
-- ending U4


-- U5: Fifth entity unit => comparator for s_lower (lower leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity comp2 is
Port ( Cin : in STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end comp2;

architecture Behavioral of comp2 is
begin
Cout<= '1' when (unsigned(Cin) > 1) else '0'; -- (Cin) > 4 is changed with (Cin) > 1
end Behavioral;
-- ending U5


-- Example 5

-- Clock FPGA APEX20KE=33.33Mhz==>t=30ns
-- This deadtime is designed =
2040ns=2microsecond
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity deadtimev5 is
Port ( clock : in STD_LOGIC;
Sin : in STD_LOGIC;
Supper : out STD_LOGIC;
Slower : out STD_LOGIC);
end deadtimev5;

architecture behavioral of deadtimev5 is
signal a,c: std_logic_vector(4 downto 0);
signal d : std_logic;


-- The deadtime's entity is supported 5 entity unit
begin
U1: entity work.mod40(Behavioral) port map(clk=>clock,clkout=>d);
U2: entity work.upper_counter(Behavioral) port map(clk=>d,clear=>Sin,uc=>a);
U3: entity work.lowr_counter(Behavioral) port map(clk=>d,clear=>Sin,lc=>c);
U4: entity work.comp1(Behavioral) port map(Cin=>a,Cout=>Supper);
U5: entity work.comp2(Behavioral) port map(Cin=>c,Cout=>Slower);
end Behavioral;


-- U1: First entity unit => counter mod17 (clock divider)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity mod40 is
Port ( clk : in STD_LOGIC;
clkout : out STD_LOGIC);
end mod40;

architecture Behavioral of mod40 is
signal q : std_logic;
signal qint1,qint2 : std_logic_vector (6 downto 0);
begin
qint1 <= "0000000" when q='1' else std_logic_vector(unsigned(qint2)+1);
qint2 <= qint1 when rising_edge(clk);
q <= '1' when (unsigned(qint2) = 68) else '0'; -- changed mod17 to mod68 (17*4)
clkout <= q;
end Behavioral;
-- ending U1


-- U2: Second entity unit => upper_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity upper_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
uc : out STD_LOGIC_VECTOR (4 downto 0));
end upper_counter;

architecture Behavioral of upper_counter is
signal qint, q : std_logic_vector(4 downto 0);
begin
qint <= (others=>'0') when clear ='0' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
uc<= q;
end Behavioral;
-- ending U2


-- U3: Third entity unit => lower counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity lowr_counter is
Port ( clear : in STD_LOGIC;
clk : in STD_LOGIC;
lc : out STD_LOGIC_VECTOR (4 downto 0));
end lowr_counter;

architecture Behavioral of lowr_counter is
signal qint, q : std_logic_vector(4 downto 0);
begin
qint <= (others=>'0') when clear ='1' else std_logic_vector(unsigned(q)+1);
q <= qint when rising_edge(clk);
lc<= q;
end Behavioral;
-- ending U3


-- U4: Fourth entity unit => comparator for s_upper (upper leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity comp1 is
Port ( Cin : in STD_LOGIC_VECTOR (4 downto 0);
Cout : out STD_LOGIC);
end comp1;

architecture Behavioral of comp1 is
begin
Cout <= '1' when (unsigned(Cin) > 1) else '0'; -- (Cin) > 4 is changed with (Cin) > 1
end Behavioral;
-- ending U4


-- U5: Fifth entity unit => comparator for s_lower (lower leg)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity comp2 is
Port ( Cin : in STD_LOGIC_VECTOR (4 downto 0);
Cout : out STD_LOGIC);
end comp2;

architecture Behavioral of comp2 is
begin
Cout<= '1' when (unsigned(Cin) > 1) else '0'; -- (Cin) > 4 is changed with (Cin) > 1
end Behavioral;
-- ending U5

Tole Sutikno - Electrical Engineering Department Copyright 2013